Application

14273483 · SEMICONDUCTOR CHIP INCLUDING REGION HAVING CROSS-COUPLED TRANSISTOR CONFIGURATION WITH OFFSET ELECTRICAL CONNECTION AREAS ON GATE ELECTRODE FORMING CONDUCTIVE STRUCTURES AND AT LEAST TWO DIFFERENT INNER EXTENSION DISTANCES OF GATE ELECTRODE FORMING CONDUCTIVE STRUC

Filed 2014-05-08 · Granted · Patent 8847331 (2014-09-30) The official file ↗The patent and its PDF ↗ · Art unit 2826 · Examiner Wensing W Kuo Typical · CPC H10D 84/907 · Tela Innovations, Inc. · PENILLA IP, APC - PATENT LAW