PATLY.AIApplication
15140327 · INTEGRATED CIRCUIT RETIMING WITH SELECTIVE MODELING OF FLIP-FLOP SECONDARY SIGNALS
Filed 2016-04-27 · Granted · Patent 10162918 (2018-12-25) The official file ↗The patent and its PDF ↗ · Art unit 2851 · Examiner Mohammed Alam Typical · CPC G06F 30/3312 · Altera Corporation · Treyz Law Group
Office actions
2
first was Non-final rejection
RCEs
0
no appeal
To first action
13.7 mo
to disposition 31.9 mo
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