Application

15413071 · METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

Filed 2017-01-23 · Granted · Patent 10170276 (2019-01-01) The official file ↗The patent and its PDF ↗ · Art unit 2851 · Examiner Brian Ngo Typical · CPC H10P 76/2041 · Taiwan Semiconductor Manufacturing Company, Ltd. · Haynes and Boone, LLP (24061)

Office actions

first was Non-final rejection

RCEs

no appeal

To first action

15.5 mo

to disposition 23.3 mo

Statutes raised

101 102

1 actions read

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