Application

16891027 · TIME BORROWING BETWEEN LAYERS OF A THREE DIMENSIONAL CHIP STACK

Filed 2020-06-02 · Granted · Patent 10970627 (2021-04-06) The official file ↗The patent and its PDF ↗ · Art unit 2822 · Examiner Ida M Soward Easy · CPC G06N 3/065 · Xcelsis Corporation · TESSERA

Office actions

first was Notice of allowance

RCEs

no appeal

To first action

6.0 mo

to disposition 10.1 mo

Statutes raised

0 actions read

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