Application

17120618 · SYSTEM AND METHOD FOR IDENTIFYING DESIGN FAULTS OR SEMICONDUCTOR MODELING ERRORS BY ANALYZING FAILED TRANSIENT SIMULATION OF AN INTEGRATED CIRCUIT

Filed 2020-12-14 · Granted · Patent 12493072 (2025-12-09) The official file ↗The patent and its PDF ↗ · Art unit 2189 · Examiner Bijan Mapar Typical · CPC G06F 30/367 · Bayes Electronics Technology Co., Ltd · MUNCK WILSON MANDALA L.L.P

Office actions

first was Non-final rejection

RCEs

no appeal

To first action

40.5 mo

to disposition 59.8 mo

Statutes raised

101 103

3 actions read

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