Application

17650250 · ASYNCHRONOUS FULL-ADDER WITH MAJORITY OR MINORITY GATES TO GENERATE SUM TRUE OUTPUT

Filed 2022-02-08 · Granted · Patent 12524205 (2026-01-13) The official file ↗The patent and its PDF ↗ · Art unit 2182 · Examiner Jonathan David Warner · CPC G06F 7/508 · Kepler Computing Inc. · MUGHAL GAUDRY & FRANKLIN PC

Office actions

first was Notice of allowance

RCEs

no appeal

To first action

42.9 mo

to disposition 47.1 mo

Statutes raised

0 actions read

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