Application

17969251 · LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT

Filed 2022-10-19 · Granted · Patent 12273117 (2025-04-08) The official file ↗The patent and its PDF ↗ · Art unit 2849 · Examiner Diana Cheng Hard · CPC H03L 7/087 · STMicroelectronics International N.V. · CROWE & DUNLEVY - ST

Office actions

first was Non-final rejection

RCEs

no appeal

To first action

22.5 mo

to disposition 29.6 mo

Statutes raised

102 103

1 actions read

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